MAX5101BEUE+【PDF 3/8 页】IC DAC 8BIT TRPL R-R 16-TSSOP

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Sheet目录2009

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MAX5101

+2.7V to +5.5V, Low-Power, Triple, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +5.5V, RL = 10k

, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and

TA = +25°C.)

Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.

Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VDD]. Where VF0,meas is the DAC output voltage with input code F0 hex, and

VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VDD 240 / 256).

Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of VOUT’s final value.

Note 4: Channel-to-Channel Isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any

other DAC output. The measured channel has a fixed code of 80 hex.

Note 5: Digital Feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight

data inputs with WR at VDD.

Note 6: RL =

∞ , digital inputs at GND or VDD.

Note 7: Timing measurement reference level is (VIH + VIL) / 2.

CONDITIONS

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

Digital-to-Analog Glitch Impulse

Code 80 hex to code 7F hex

nVs

Wideband Amplifier Noise

VRMS

Shutdown Recovery Time

tSDR

To ±1/2LSB of final value of VOUT

Time to Shutdown

tSDN

IDD < 5A

Power-Supply Voltage

VDD

2.7

5.5

Supply Current (Note 6)

IDD

280

520

Shutdown Current

Address to WR Setup

tAS

Address to WR Hold

tAH

Data to WR Setup

tDS

WR Pulse Width

tWR

Data to WR Hold

tDH

POWER SUPPLIES

DIGITAL TIMING (Figure 1) (Note 7)

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